By Robert Lanzone (auth.), Ho-Ming Tong, Yi-Shao Lai, C.P. Wong (eds.)
Advanced turn Chip Packaging provides previous, current and destiny advances and tendencies in components similar to substrate expertise, fabric improvement, and meeting techniques. turn chip packaging is now in common use in computing, communications, buyer and automobile electronics, and the call for for turn chip expertise is continuous to develop for you to meet the necessity for items that supply larger functionality, are smaller, and are environmentally sustainable.
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Additional info for Advanced Flip Chip Packaging
Tong et al. 1007/978-1-4419-5768-9_2, # Springer Science+Business Media New York 2013 23 24 E. Perfecto and K. Srivastava Fig. 1 High Lead solder on an IC (IBM, 1970) Heat sinks Chip-1st level interconnect Capacitors Heat spreaders 1st level packages organic, ceramic Printed Wiring Board (PWB) Thermal Interface Materials 2nd level interconnect Fig. 2 First level package elements initially joined mainly to ceramic substrates utilizing leaded solders. The introduction of surface laminar circuit (SLC) enabled the organic carriers to increase the wiring density and pitch making it the preferred chip carrier .
By using these package as an integration fabric to combine one or more ICs with discrete, embedded, and other packaged parts, a module can be created and used as a standard component for a POP assembly. From a reliability perspective the PoP and PiP have shown that they can have a ball count of ~300 for 10 Â 10 mm packages and ~600 for 15 Â 15 mm packages and can have a junction temperature, Tj, as high as 110 C. There is a need to improve/control package warpage to about 60 mm by materials and structural design.
The ITRS has defined the “More Moore” applications to those where functional and performance scaling are enabled by both geometrical and equivalent scaling. Geometrical scaling refers to the vertical and horizontal shrinkage of features on the chip associated with speed and power advancements, while equivalent scaling refers to 3-dimensional device structures which complements geometrical scaling and enhances the electrical performance of the chip . “More than Moore” integrates the More Moore innovations with the non-scaling technologies (such as analog/RF, passives, HV sensors, actuators and biochips) to produce high value system through functional diversification.